The demand for more reliable integrated circuit components for use in communication, instrumentation and high-quality video applications continues to increase. As a result, integrated circuit manufacturers are requiring for such components and devices to meet the design requirements of a myriad of emerging applications. In particular, integrated circuit manufacturers are requiring analog-to-digital converters and related components to continue to improve data rates, noise reduction, and accuracy.
A popular technique for implementing analog-to-digital converters includes the use of delta-sigma modulation wherein an analog voltage is input to a delta-sigma modulator. Such modulators produce noise, e.g., quantization and thermal noise, which must be filtered out by the digital filter. The digital filter generally uses decimation in the filtering process, with the result that the digital data is processed at a much slower rate than the output rate of the modulator, e.g., by digitally converting the sampling rate of the signal from a given rate to a lower rate. This filtering process is generally operable to remove large amounts of noise at the cost of reducing the bandwidth of the analog-to-digital converter.
While these delta-sigma analog-to-digital converter techniques can provide lower noise characteristics, these techniques can result in slower settling times, i.e., present techniques, although capable of reducing noise, can provide increases in the response time of the digital filter resulting from changes in the input signal, and thus have an undesirable amount of delay before valid data is provided to the analog-to-digital converter.
One approach for improving the settling time is disclosed in U.S. Pat. No. 5,777,911, for “Digital Filtering System”, issued Jul. 7, 1998 to Sherry et al. (“Sherry reference”). The Sherry reference discloses the use of two filters configured in series, wherein the first filter is configured to operate at a fixed rate while the second filter is configured to operate at an adjustable rate. During operation, the second filter is receiving output samples from the first filter and averaging those samples to provide an averaged output signal. This operation can result in an increased settling time, but also with a higher resolution. As the input signal provides a step change, the step change is detected at the output of the first filter. As a result, the second filter will flush the currently averaged samples, and thereafter begin sampling and averaging only the new data using a faster settling time.
While the Sherry reference discloses a technique which attempts to address the above problems regarding the increased settling time of digital filters, there are drawbacks. For example, the technique uses two filters operating in series, with the first filter operating at a fixed rate having an undesirable additional delay. To address this additional delay, the Sherry technique requires that the modulator, in addition to the second filter, operate at a higher data rate, which results in higher power consumption.
With reference to FIG. 1, a block diagram of a multiplexed, delta-sigma modulator and digital filter for an analog-to-digital converter is illustrated. A multiplexor 102 is coupled with multiple input channels to provide an output from the selected input channel to a modulator 104 and a digital filter 106. A problems arises as the input channel is switched at multiplexor 102. When this switching of input channels occurs, the analog-to-digital converter must wait for digital filter 106 to settle before valid data can be received and processed. Digital filter 106 can comprise various types of filters having a built-in delay. For example, digital filter 106 can comprise a sincx-type filter, such as a sinc3-type filter disclosed by E. B. Hogenauer in “An Economical Class of Digital Filters for Decimation and Interpolation”, IEEE Transmission, Acoustics, Speech, Signal Processing, vol. ASSP-29, pp. 155–162, April 1981.
Accordingly, while the input channel can be switched from a first channel to a second channel to receive new input data signals, the analog-to-digital converter must wait for the settling time of the digital filter to be completed before accurate data can be received from a different input channel. This delay in waiting for valid data can be greatly affected by the type of modulator 104 selected, which dictates the group delay of digital filter 106. For example, in many applications the group delay can be 4 or 5 or more, such as applications requiring a sinc-type filter comprising a four or higher-delay filter that needs four or five cycles to settle before valid data can be read.
Other attempts for providing a faster response or more accurate digital filter have included the implementation of a faster settling sinc1 filter in addition to a default sinc3 filter, wherein the user can toggle between the two sinc filters depending on whether the application requires faster settling and less accuracy or slower settling and higher accuracy. However, such an approach does not provide a smooth transition between the two filters, but instead provides, at best, an option between a faster settling and lower resolution filter or a slower settling and higher resolution filter, rather than a composite filter including characteristics of both filters.
Accordingly, a need exists for a fast-settling digital filter technique and circuit for facilitating a faster response time to changes in the input channel of multiplexed, delta-sigma analog-to-digital filter.